Dewey CutterNumber :
/73 19
Title :
Logic minimization algorithms for VLSI synthesis
Author Statement :
by Robert K. Brayton ... [et al.]
Publication :
Kluwer Academic Publishers
Collation :
ix, 192 p. : ill. ; 25 cm
Series :
The Kluwer international series in engineering and computer science ; SECS 2. VLSI, computer architecture, and digital signal processing.
Subject :
Logic design,Integrated circuits -- Very large scale integration,Integrated circuits -- Design and construction -- Data processing,Algorithms
ADDED ENTRIES :
Brayton, Robert King,Title: Logic minimization algorithms for V.L.S.I. synthesis
Holding Info. :
0898381649
Biblography :
Bibliography: p. [174]-190.
