Author :
Bergeron, Janick
Title :
Writing testbenches using System Verilog
Author Statement :
by Janick Bergeron
Collation :
xxvi, 412 p. : ill. ; 25 cm
Notes :
This book presents the same concepts as the second edition of Writing testbenches, functional verification of HDL models, but uses System Verilog as the sole implementation vehicle. The languages used in the second edition are still available
Subject :
Computer hardware description languages , Integrated circuits
ADDED ENTRIES :
Bergeron, Janick
Index :
Includes bibliographical references and index
