تراشه ي بينايي مبتني بر پردازنده هاي سطري/ستوني

چكيده انگليسي :

Vision Chip Based On Row Column Processors Mohammad Hasan Davari mh davary@ec iut ac ir Date of Submission Department of Electrical and Computer Engineering Isfahan University of Technology Isfahan 84156 83111 Iran Degree M Sc Language FarsiSupervisor Dr Sayed Masoud SayediAbstractToday vision chips have many applications in real time image processing By integrating the imagesensor and processor s on one substrate the data transfer bottleneck between these two parts hasbeen removed and as a result the chips are capable of performing image processing algorithms atvery high frame rates in order of thousands frames per second Different types of vision chips eachwith its own pros and cons have been proposed and fabricated and are categorized based ondifferent parameters For instance they can be categorized based on their circuit structures asanalog or digital vision chips Digital vision chips are faster more robust and more tolerant to thenoise On the other hand analog ones consume less power and are more compact Processorsarrangement is another parameter used to group these chips Processors can be located next to eachpixel or next to each column row of pixels or next to entire pixels array Pixel level processors arethe fastest but they are extremely large and reaching to high resolution images are impossible withthem In contrast chip level processors are a good choice for high resolution images but they arerelatively slow Column level processors are located between these two limits In this work ageneral purpose vision chip based on column processors is proposed The vision chip uses SIMDstructure for its image parallel processing By using digital processors the chip can process blackand white binary and gray 8 bit images Image algorithms implemented in this chip are low level and include spatial filter with a 5 5 kernel and with arbitrary coefficients like edge detectionand averaging ranking or statistical filter like median maximum and minimum filters andmorphological filter including erosion and dilation By exploiting a global memory the chip area isreduced and also performing high frame rate image processing tasks is possible The processing isdone in a bit serial manner due to the large size of the kernels The proposed structure can be easilydeveloped for doing other tasks There is a processing element PE and it s corresponding circuitfor each 5 column of the pixels array Therefore the size of the chip is proportional to the numberof image columns while the processing speed is proportional to the number of images rows Forexample it takes 40 s and 4 8 s to process an image with 64 rows in gray and binary moderespectively The proposed circuit is implemented using both full costum design and digital designflow manner The SDF files are used for time verification of the circuits The results related todesign implementation and simulation of a 64 64 array verifiy the functionality of the circuit Keywords 1 vision chip 2 CMOS image computing sensor 3 VLSI 4 row column processors5 image processing 6 SDF Files

داوري، محمدحسن

تراشه ي بينايي مبتني بر پردازنده هاي سطري/ستوني

حسگر محاسباتي تصوير CMOS , VLSI , پردازش تصوير , فايل SDF