توصيفگر ها :
مبدل زمان به ديجيتال , تقويت‌كننده زمان , حلقه قفل فاز تمام ديجيتال , اينترنت اشيا , بلوتوث كم‌توان
چكيده فارسي :
ﺑﻠﻮﺗﻮﺙ ﮐﻢﺗﻮﺍﻥ (BLE) ﺍﺯ ﻣﺤﺒﻮﺏﺗﺮﯾﻦ ﺍﺳﺘﺎﻧﺪﺍﺭﺩﻫﺎﯼ ﺑﯿﺴﯿﻢ ﮐﻮﺗﺎﻩ ﺑﺮﺩ ﺩﺭ ﺑﺎﻧﺪ ISM GHz4̸2 ﺍﺳﺖ ﮐﻪ ﺩﺭ ﮐﺎﺭﺑﺮﺩﻫﺎﯼ ﺍﯾﻨﺘﺮﻧﺖ ﺍﺷﯿﺎ (IoT) جايگاه مهمي ﭘﯿﺪﺍ ﮐﺮﺩﻩ ﺍﺳﺖ. ﺩﺭ ﭼﻨﯿﻦ ﺍﺳﺘﺎﻧﺪﺍﺭﺩﯼ ﮐﺎﻫﺶ ﺗﻮﺍﻥ مصرفي سنتزكننده ﻓﺮﮐﺎﻧﺲ، ﮐﻪ ﺩﺭ شرايطي حتي ﺑﯿﺶ ﺍﺯ 50 ﺩﺭﺻﺪ ﺍﺯ ﺳﻬﻢ ﺑﻠﻮﮎ ﭘﺮ ﻣﺼﺮﻑ ﻓﺮﺳﺘﻨﺪﻩ ﻭ ﮔﯿﺮﻧﺪﻩ ﺭﺍﺩﯾﻮﯾﯽ ﺭﺍ ﺩﺭ ﺑﺮ مي‌گيرد، ﺗﻮﺟﻪ ﺯﯾﺎﺩﯼ ﺭﺍ ﺩﺭ ﺳﺎﻝﻫﺎﯼ ﺍﺧﯿﺮ ﺍﺯ ﻣﺤﻘﻘﯿﻦ ﺑﻪ ﺧﻮﺩ ﺍﺧﺘﺼﺎﺹ ﺩﺍﺩﻩ ﺍﺳﺖ. ﺍﺯ ﻣﻬﻤﺘﺮﯾﻦ ﺗﻼﺵﻫﺎﯾﯽ ﮐﻪ ﺍﺧﯿﺮﺍ ﺩﺭ ﮐﺎﻫﺶ ﺗﻮﺍﻥ مصرفي ﺳﻨﺘﺰكنندهﻫﺎﯼ ﻓﺮﮐﺎﻧﺲ ﺻﻮﺭﺕ ﮔﺮﻓﺘﻪ ﺟﺎيگزيني ﺍﻟﻤﺎﻥ ﭘﺮ ﻣﺼﺮﻑ ﺣﻠﻘﻪ ﻗﻔﻞ ﻓﺎﺯ (PLL) آنالوگي ﺑﺎ ﺣﻠﻘﻪ ﻗﻔﻞ ﻓﺎﺯ ﺗﻤﺎﻡ ﺩﯾﺠﯿﺘﺎﻝ (ADPLL) ﺑﻮﺩﻩ ﺍﺳﺖ. يك PLL ﺁﻧﺎﻟﻮﮒ ﻋﻼﻭﻩ ﺑﺮ ﺁﻧﮑﻪ ﻣﺴﺎﺣﺖ ﺯﯾﺎﺩﯼ ﺍﺯ ﺗﺮﺍﺷﻪ ﺍﺷﻐﺎﻝ مي‌كند ﻭ ﺑﺎ ﭘﯿﺸﺮﻓﺖ ﺗﮑﻨﻮﻟﻮﮊﯼ ﻧﯿﺰ ﺍﻧﻄﺒﺎﻕ نمي‌يابد، ﻣﻌﻤﻮﻻ ﺑﺮﺍﯼ ﺩﺳﺘﯿﺎﺑﯽ ﺑﻪ سطح ﺟﯿﺘﺮ ﻣﻄﻠﻮﺏ ﺍﺳﺘﺎﻧﺪﺍﺭﺩ BLE ﺗﻮﺍﻥ ﺯﯾﺎﺩﯼ ﻧﯿﺰ ﻣﺼﺮﻑ مي‌كند. ﺑﻨﺎﺑﺮﺍﯾﻦ ﺩﺭ ﺑﺴﯿﺎﺭﯼ ﺍﺯ ﮐﺎﺭﺑﺮﺩﻫﺎ PLLﻫﺎﯼ ﺁﻧﺎﻟﻮﮒ ﺟﺎﯼ ﺧﻮﺩ ﺭﺍ ﺑﻪ ADPLLﻫﺎ ﺩﺍﺩﻧﺪ ﻭ ﺍﯾﻦ ﺭﻭﻧﺪ ﺩﺭ ﺳﺎﻝﻫﺎﯼ ﺍﺧﯿﺮ ﺳﺮﻋﺖ ﺑﯿﺸﺘﺮﯼ ﻧﯿﺰ ﮔﺮﻓﺘﻪ ﺍﺳﺖ. ﺍﯾﻦ جايگزيني ﺭﺍ مي‌توان ﺍﻧﻘﻼﺑﯽ ﻣﻬﻢ ﺩﺭ ﮔﺮﺩﺁﻭﺭﯼ شبكه‌هاي ﺑﯿﺴﯿﻢ ﺭﺷﺪ ﯾﺎﻓﺘﻪ ﺗﺤﺖ ﺍﺳﺘﺎﻧﺪﺍﺭﺩ BLE ﻧﺎﻣﯿﺪ. ﺑﺎ ﺍﯾﻦ ﻭﺟﻮﺩ جايگزيني ﺍﺧﯿﺮ مشكلات ﺯﯾﺎﺩﯼ ﺭﺍ ﺧﻠﻖ ﮐﺮﺩﻩ ﺍﺳﺖ. ﺍﺯ ﺟﻤﻠﻪ ﺁﻧﻬﺎ مي‌توان ﺑﻪ ﻗﺪﺭﺕ تفكيك ﻣﺤﺪﻭﺩ ﻧﻮﺳﺎﻧﮕﺮ ﮐﻨﺘﺮﻝﺷﻮﻧﺪﻩ ﺩﯾﺠﯿﺘﺎﻝ (DCO) ﻭ ﻣﺒﺪﻝ ﺯﻣﺎﻥ ﺑﻪ ﺩﯾﺠﯿﺘﺎﻝ (TDC) ﺑﻪ ﻋﻨﻮﺍﻥ ﺩﻭ ﺑﻠﻮﮎ اصلي ADPLL ﺍﺷﺎﺭﻩ ﮐﺮﺩ ﮐﻪ ﺑﺎﻋﺚ ﺗﻀﻌﯿﻒ عملكرد ﻧﻮﯾﺰ خروجي ﻧﺴﺒﺖ ﺑﻪ PLL آنالوگي ﺷﺪﻩ ﺍﻧﺪ. ﻣﻌﻤﻮﻻ ﺑﺎ ﮐﺎﻫﺶ ﺑﻬﺮﻩ DCO ﻭ ﯾﺎ ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ ﺩﺍﯾﺘﺮﯾﻨﮓ مي‌توان ﻗﺪﺭﺕ تفكيك DCO ﺭﺍ ﺍﻓﺰﺍﯾﺶ ﺩﺍﺩ ﺍﻣﺎ ﻣﺘﺎﺳﻔﺎﻧﻪ ﻗﺪﺭﺕ تفكيك TDC ﻫﻤﭽﻨﺎﻥ ﺩﺭ ﺳﺎﻝﻫﺎﯼ ﺍﺧﯿﺮ ﻋﺎﻣﻞ اصلي ﺩﺭ ﺗﻀﻌﯿﻒ عملكرد ﺟﯿﺘﺮ خروجي ﺑﻮﺩﻩ ﺍﺳﺖ. ﺍﺯ ﻃﺮﻑ ديگر ﻣﻌﻤﻮﻻ ﺑﯿﻦ ﻗﺪﺭﺕ تفكيك ﻭ ﺗﻮﺍﻥ مصرفي TDC ﻧﯿﺰ ﺭﺍﺑﻄﻪ ﻋﮑﺲ ﻭﺟﻮﺩ ﺩﺍﺭﺩ ﮐﻪ ﺑﻪ ﭼﺎﻟﺶﻫﺎﯼ طراحي ﺗﻮﺍﻥ ﭘﺎﯾﯿﻦ TDC ﺩﺭ ﮐﻨﺎﺭ سطح ﻧﻮﯾﺰ ﻣﻄﻠﻮﺏ خروجي ﺍﻓﺰﻭﺩﻩ ﺍﺳﺖ. ﺩﺭ ﺍﯾﻦ ﭘﺎﯾﺎﻥﻧﺎﻣﻪ نوعي TDC ﺗﻤﺎﻡ ﺩﯾﺠﯿﺘﺎﻝ ﺑﺎ ﻗﺪﺭﺕ تفكيك ﺑﺎﻻ ﺑﺮﺍﯼ ADPLL انباشتي ﺭﺍ ﭘﯿﺸﻨﻬﺎﺩ مي‌دهيم ﮐﻪ ﺩﺭ ﺁﻥ ﺧﻄﺎﯼ ﻓﺎﺯ ﻭﺭﻭﺩﯼ ﺗﻮﺳﻂ يك ﭘﯿﺶ ﺗﻘﻮﯾﺖﮐﻨﻨﺪﻩ ﺯﻣﺎﻥ (TⅮA) ديجيتالي ﺑﺎ ﮔﺴﺘﺮﻩ ديناميكي خطي ﻭ ﺑﻬﺮﻩ ﺑﺎﻻ ﻭ يك ﺷﻤﺎﺭﻧﺪﻩ ذاتي ADPLL انباشتي ﺑﻪ ﺩﯾﺠﯿﺘﺎﻝ ﺗﺒﺪﯾﻞ مي‌شود. ﺍﺳﺘﻔﺎﺩﻩ ﺍﺯ سيگنال ﺳﺎﻋﺖ DCO ﺑﻪ ﻋﻨﻮﺍﻥ ﻓﺮﮐﺎﻧﺲ مرجع ﺷﻤﺎﺭﻧﺪﻩ ﻧﯿﺎﺯ ﺑﻪ ﺑﻬﻨﺠﺎﺭﺳﺎﺯﯼ ﺧﻄﺎﯼ ﮐﺴﺮﯼ ﻓﺎﺯ ﺭﺍ ﺍﺯ ﺑﯿﻦ ﺑﺮﺩﻩ ﻭ TDC ﭘﯿﺸﻨﻬﺎﺩﯼ ﺭﺍ ﻋﺎﺭﯼ ﺍﺯ ﻣﺪﺍﺭ ﺗﻌﯿﯿﻦ ﺩﻭﺭﻩ DCO ﻧﻤﻮﺩﻩ ﺍﺳﺖ. ﻫﻤﭽﻨﯿﻦ ﺍﺳﺘﻔﺎﺩﻩ ﺩﻭﮔﺎﻧﻪ ﺍﺯ ﺷﻤﺎﺭﻧﺪﻩ ذاتي ADPLL ﻧﯿﺎﺯ ﺑﻪ يك ﺷﻤﺎﺭﻧﺪﻩ ﻣﺠﺰﺍ ﺭﺍ ﻧﯿﺰ ﺣﺬﻑ ﮐﺮﺩﻩ ﻭ ﺑﻪ ﮐﺎﻫﺶ ﻣﺴﺎﺣﺖ TDC ﺍﻧﺠﺎﻣﯿﺪﻩ ﺍﺳﺖ. ﺍﺭﺯﯾﺎﺑﯽ ﻃﺮﺡ ﭘﯿﺸﻨﻬﺎﺩﯼ ﺩﺭ ﺗﮑﻨﻮﻟﻮﮊﯼ سي ﻣﺎﺱ nm65 ﻭ ﺍﺑﺰﺍﺭ ﺗﺤﻠﯿﻞ Spectre ﺍﺯ ﻣﺠﻤﻮﻋﻪ Cadence ﺻﻮﺭﺕ ﮔﺮﻓﺘﻪ ﺍﺳﺖ.
چكيده انگليسي :
The short-range wireless standard backed up by 2.4GHz ISM band has reaped rewards from the mainstay, crowd-favoring Bluetooth Low Energy (BLE) standard over the last decades. The BLE has allowed profound applications in the
Internet of Things (IoT) industry. The standard is now drawing meticulous attention from researchers, particularly in the
area of low-power design of frequency synthesizers, which are considered as the power bottleneck of the radio transceivers.
The continuous replacement of All Digital Phase Locked Loops (ADPLL) with their power-demanding analog counterparts,
namely analog PLLs, accounts for the most successful attempts to date at addressing power-inefficiency issues involved in
frequency synthesizers. The technology-unfriendly analog PLLs not only take up a large area of the die, but also consume
a lot of power to meet the low-level jitter demand required by the BLE standard. That said, analog PLLs cannot sustain a
competition with state-of-the-art sub-mW ADPLLs in low-power IoT applications relying on energy-harvesting techniques
to provide for their energy. Even though the recent revolutionary takeover has made it possible to put together wireless
networks grown up under the BLE standard, it has led to many critical side effects that require careful investigation. Among
many, one can refer to the weakened output phase noise compared to the analog PLL’s as a result of the finite resolution
of the Digitally Controlled Oscillator (DCO) and of the Time to Digital Converter (TDC) as two backbones of the ADPLL
system. Usually the former could be ameliorated either by decreasing DCO gain or using dithering technique, whereas the
latter has still continued to put a limit on the minimum output phase noise in recent years. Besides, a lower power design goal
has to be inevitably traded off for a higher output jitter level, making it even more challenging to satisfy the BLE standard
for power-limiting IoT applications. In the present work we put forward an all-digital, high-resolution TDC suitable for
accumulated-based ADPLLs where phase error is measured by a large dynamic range, high-gain, digitally-made Time to
Digital Amplifier (TDA) followed by the ADPLL’s built-in accumulative high frequency counter. Re-using the DCO clock
as the counter’s reference frequency removed the need for a separate circuit for normalizing fractional phase error, allowing
the proposed TDC to enjoy a DCO period detection free mechanism. Moreover, re-using the ADPLL’s built-in counter
eliminated a standalone counter that would have otherwise been needed, and, as a result, some space were freed up for more
useful circuitries on the die. The proposed TDC is built and tested in TSMC 65nm CMOS technology using Spectre analysis
tool as part of the Cadence design system.
