طراحي و پياده سازي شتاب‌دهنده سخت‌افزاري مبتني بر مدل YOLOv3-tiny براي تشخيص اشيا به صورت بلادرنگ

With the rapid growth of computer vision applications in real-time an‎d edge-based systems, the need for efficient implementation of object detection algorithms with low power consumption an‎d low latency has become increasingly important. Despite their high accuracy, deep object detection networks face significant challenges when deployed directly on general-purpose processors due to their high computational complexity an‎d substantial processing resource requirements. In this context, FPGA-based hardware accelerators have attracted considerable attention as a flexible an‎d energy-efficient solution. In this thesis, a real-time object detection system based on the YOLOv3-tiny network is designed an‎d implemented as a hardware accelerator on an FPGA platform. First, the structure of the YOLOv3-tiny network is thoroughly analyzed an‎d fully implemented in software. By simulating the software model, the computational bottlenecks of the network are identified. To improve network efficiency, techniques such as data an‎d weight quantization, convolution operation parallelization, modular design, an‎d memory access optimization are proposed, an‎d their effectiveness is eva‎luated using the developed software model. After obtaining a suitable design based on software simulations, a custom hardware architecture is developed to accelerate the network. At this stage, additional strategies are introduced to overcome the limitations of available hardware resources. The proposed hardware accelerator is implemented on the Xilinx Kria KV260 board, an‎d the performance of its main components, including data input, filtering, processing, an‎d output units, is thoroughly eva‎luated. The accelerator is validated using stan‎dard eva‎luation metrics, including detection accuracy, frame rate, hardware resource utilization, an‎d power consumption. Experimental results demonstrate that the proposed architecture achieves a processing speed of 66 frames per second with a power consumption of approximately 3.4 W, while maintaining acceptable detection accuracy, an‎d delivers superior performance compared to similar works reported in the literature. Moreover, the modular an‎d flexible structure of the proposed architecture enables its extension an‎d adaptation to other convolutional neural networks an‎d real-time edge-oriented applications.

وحيد غفاري نيا , حسين نيك ائين

حسين فرزانه فرد , مسعود سيدي