3499

3305

كارشناسي ارشد

الكترونيك

اصفهان: دانشگاه صنعتي اصفهان، دانشكده برق و كامپيوتر

1385

ده، 135، [II]ص.: مصور، جدول، نمودار

ص. ع. به فارسي و انگليسي

مسعود سيدي

رسول دهقاني

1/3/86

1396/02/30

كتابنامه

برق و كامپيوتر

مهندسي برق و كامپيوتر

ID3305

به فارسي و انگليسي: قابل رويت در نسخه ديجيتال

Abstract Pipelined Analog to Digital Converters ADCs are used extensively in high speed andhigh resolution applications such as wireless communications video and graphics andimage recognition In this architecture like most of analog systems there is a strong trade off between speed and resolution so finding the ways to moderate this trade off is one ofthe main challeneges in the literature Time interleaving structures have the advantage ofincreasing the throughput rate of PADCs however they suffer from many problems due tothe time multiplexing and mismatching of the channels that significantly limit the effectivebandwidth of the input signal Recently digital calibration methods have been proposed tomoderate the above mentioned speed accuracy trade off by shifting the analog complexityinto a digital section It allows imperfect design to have a high speed structure and postprocessing to increase the resolution Obviously sacrificing the other two main ADCfactors power and area may happen which is tolerable in many applications This thesis presents a background calibration technique in which linear and offset errorsare digitally measured and eliminated The proposed structure keeps the nonlinear errors inlow values moreover the algorithm is easily extendable to cover this source of error Theproposed technique utilizes a single algorithm and works in real time without tamperingwith analog signal paths which is inevitable in many conventional approaches Consequently the proposed algorithm can moderate the speed accuracy trade off in the bestmanner and the ADC can maintain maximum conversion speed and resolution within acertain technology

مسعود سيدي

رسول دهقاني