بررسي ساختارها و پياده سازي بلوك هاي FEC در استاندارد WiMax روي FPGA

چكيده انگليسي :

A Study of Architectures and Implementation of WiMax FEC blocks on FPGA Ali Masoudi masoudi@ec iut ac ir Date of Submission 2009 10 6 Department of Electrical and Computer Engineering Isfahan University of Technology Isfahan 84156 83111 Iran Degree M Sc Language FarsiSupervisor Mohammad Javad Omidi omidi@cc iut ac irAbstract Since the invention of wireless telegraphy by Marconi in 1897 wireless technology has not only beenenhanced but also has become an essential part of our everyday lives In years wireless technology has beenexpanded more and more The first wireless mobile phone invented around 1980 In wireless networking IEEE 802 11 also known as WiFi was the first standard released in 1997 but IEEE 802 11b 1999 is knownas the first wireless networking standard that was widely accepted IEEE 802 15 also known as PAN wascreated in 2003 and IEEE 802 16 also known as WiMax is the latest standard for mobile and fixed wirelesscommunication approved in 2004 Unlike its short range predecessors 802 11 and 802 15 WiMax has longerrange up to 50 km The most popular implementation of the IEEE 802 16 standard is the Mobile WirelessMAN technically proposed by the IEEE 802 16e 2005 amendment WiMax uses broadband communicationmethods like orthogonal frequency division multiplexing and it has significant advantages such as high datarates in addition to long range of operability The receiver design of WiMax involves many challenges because of wireless channel nature Implementation problems lower WiMax performance WiMax standard has several blocks in physical layer Forward Error Correction block FEC is one of the most important blocks of physical layer for WiMax FECblock includes a randomizer and a viterbi decoder Viterbi decoder has significant delay and uses largememory blocks Various methods in the literature are available for implementation of viterbi decoder In this thesis important blocks in WiMax PHY with their functions are explained Then after a surveyof different problems in implementation of WiMax FEC block different methods for design andimplementation of viterbi decoder are studied Afterwards different methods for implementation of viterbisuch as Register Exchange RE Trace Back TB and Hybrid methods are compared and for clarification ofdifferences between these methods advantages and disadvantages of them are highlighted Parameters usedfor comparison are memory usage delay processing speed and power RE method has high processing speedand low delay but it uses large memory blocks Unlike RE method TB method has lower processing speedand higher delay but it has low memory usage There is a tradeoff between memory usage and delay soHybrid methods try to gather advantages of both RE and TB methods Here we use a modified RE MRE method as an optimal method for design and implementation of FECthat has low delay and low memory usage and we proposed a new hardware combined of MRE method witha special normalizer Details of inner blocks of proposed hardware and related simulation results arediscussed Several choices for hardware like FPGAs and DSPs are compared and reasons for selection ofFPGA as implementation platform are explained Finally hardware for FEC block of WiMax is implementedon XC3S400 of Xilinx FPGAs using Verilog HDL language and the results are brought in this thesis Keywords IEEE 802 16 FEC Implementation Viterbi Decoder

مسعودي، علي

بررسي ساختارها و پياده سازي بلوك هاي FEC در استاندارد WiMax روي FPGA

استاندارد 802.16e , كد بردار ويتربي