پديد آورنده :
ناصري، سروش
عنوان :
طراحي و پياده سازي پردازنده ابر مقياسي عام منظوره و بهبود عملكرد آن با استفاده از ساختارهاي قابل پيكربندي
مقطع تحصيلي :
كارشناسي ارشد
گرايش تحصيلي :
معماري كامپيوتر
محل تحصيل :
اصفهان: دانشگاه صنعتي اصفهان، دانشكده برق و كامپيوتر
صفحه شمار :
ده، 114ص: مصور، جدول، نمودار
يادداشت :
ص.ع. به: فارسي و انگليسي
استاد راهنما :
مسعود رضا هاشمي، كيارش بازرگان
استاد مشاور :
رسول امير فتاحي
توصيفگر ها :
ريزپردازنده , پردازش چند رشته اي , حافظه نهان
تاريخ نمايه سازي :
21/11/88
دانشكده :
مهندسي برق و كامپيوتر
چكيده فارسي :
به فارسي و انگليسي: قابل رويت در نسخه ديجيتال
چكيده انگليسي :
115 Design and Implementation of a General Purpose Superscalar Processor And Improving its Performance using Reconfigurable Strctures Soroosh Nasseri Soroosh ns@yahoo com Date of Submission July 8 2009 Department of Electical and computer engineering Isfahan University of Technology Isfahan 84156 83111 Iran Degree M Sc Language FarsiSupervisor Masoud Reza Hashemi hashemim@cc iut ac irAbstractThe popularity of information and communication technology increases the demand for more powerfulprocessing and communication systems Microprocessors as one of the main parts of information systems play important role in determining the performance of these systems As a result improving the performanceand functionality of the processors will have a great effect on the performance of information processingsystems In this thesis several basic changes to the structure of a general purpose superscalar microprocessor areinvestigated in order to improve its performance and computational power The most important changes are improving the system behavior by employing the reconfigurability and working in single dual thriple andquadruple threaded modes based on the number of tasks needed to be executed by the system change in themanagement strategy of branch instructions using instruction fetch from both directions of execution improving the number of executable instructions removing upper levels of caches and reducing theperformance gap between the memory and processor In this thesis all of the design and implementation steps and the way of applying the above changes in theprocessor structure are investigated In order to quantify the efficiency of the above changes performance ofthe proposed processor in performing a set of benchmarks is compared to the performance of some selectedprocessors that represent different families of general purpose processors Based on the performance resultsof executing benchmark set performance of the proposed processor in executing integer benchmarks is betterthan the selected processors in almost all cases due to the removal of prediction in management of branchinstructions and thus reducing of their performance overhead increasing the number of executableinstructions and the ability to extract more parallelism in instruction level and also decreasing theperformance gap between processor and main memory As a result of loop based nature of floating point applications and more locality in their data accesses theimpact of applying the above changes is decreased The more advanced structure of floating point functionalunits in selected processors results in their relative superiority to the proposed processor in performingfloating point benchmarks Performance of the proposed processor in performing floating point benchmarkscan be improved using newer and more powerfull functional units Finally the proposed processor shows acceptable performance in performing benchmark applications andthis highlights the impact of applied changes in its structure After performing many tests and removing all ofthe defects in the structure of proposed processor in case of financial support it can be produced and used asa replacement to the older processors in information systems Key words Microprocessor Superscalar Processors Reconfigurability Multi Thread Processing Cache Memory
استاد راهنما :
مسعود رضا هاشمي، كيارش بازرگان
استاد مشاور :
رسول امير فتاحي