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چكيده انگليسي :

Mapping and Routing Algorithms for a New Hybrid NoC Architecture Mahsa Mousavi mh mousavi@ec iut ac ir Date of Submission 2011 05 16 Department of Electrical and Computer Engineering Isfahan University of Technology Isfahan 84156 83111 Iran Degree M Sc Language FarsiSupervisor Pejman Khadivi Kiarash Bazargan pkhadivi@cc iut ac ir kia@umn eduAbstractWith recent developments in semiconductor industry it is now possible to put various components of asystem with hundreds of processors on a single chip Network on Chip NoC has been recently presented asa promising solution to complex on chip communication problems NoCs are composed by a set of routersinterconnected by communication channels In direct NoC topologies each router connects to a module andboth are placed inside a limited region of an integrated circuit called tile Performance scalability modularityand communication parallelism make NoCs a promising communication resource for future SoCs Latency ofsystems on chip greatly depends on the communication infrastructure Therefore using low latencycommunication structures is inevitable The general trend of on chip network design includes generation ofcharacteristic graph application selecting the appropriate processing cores mapping the tasks of applicationsto the selected processing cores mapping processing cores on network on chip tiles task scheduling andselection of routing algorithm Topology and mapping algorithm are two important factors that have greatimpacts on system s latency In this thesis a new topology with the aim of latency optimization is proposed This topology is a combination of NoC and bus which can use benefits of both of these architectures Basedon some general considerations different preliminary topologies were suggested among them one topologyselected as the best topology In the proposed approach buses involve in global communications in additionto local communications A new routing algorithm is proposed that combines XY routing algorithm with thedeployment of bus for global communications A new method for application mapping is proposed for thenew hybrid architecture In this method cores with heavy affinity are placed in same bus According to thetopology and with the aim of latency reduction cores are mapped to network on chip topology The proposedalgorithm has two steps In the first step partition graph is created and mapped to buses Partition graphpresents the partitions and relations between them In the second step cores are mapped to tiles We useTGFF tool to create task graph TGFF is one of the most popular tools that is employed for task graphgeneration and also used in NoC researches For multiple use case applications with multiple task graphs weuse average graph which is created from multiple task graphs Proposed topology and mapping algorithmwas investigated in various task graph sizes For each test scenario ten task graphs were generated and theaverages results for these graphs are presented Comparison between the total communications of preliminarytopologies shows that our selected topology is the best one We also investigate our topology and mappingalgorithm with different bus bandwidth and different task graph sizes The proposed topology and mappingalgorithm results show significant improvement in contrast with conventional mapping algorithms on meshtopology Keywords Network on Chip Topology mapping keyword System on Chip

موسوي، مهسا

ارائه ي يك معماري مبتني بر تركيب باس و شبكه روي تراشه جهت سيستم هاي روي تراشه و توسعه ي الگوريتم نگاشت و مسير يابي در آن

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