بكارگيري عناصر لچ در سنتز سطح بالاي مدارهاي ديجيتال

چكيده انگليسي :

Employing Latch Elements in High Level Synthesis of Digital Circuits Elahe Sadat Banimi e banimi@ec iut ac ir Date of Submission 2011 11 14 Department of Electrical and Computer Engineering Isfahan University of Technology Isfahan 84156 83111 Iran Degree M Sc Language FarsiSupervisor Sayed Masoud Sayedi m sayedi@cc iut ac irAbstract In the last few decades high level synthesis has stabilized its position in the design automationhierarchy and due to its capability of accelerating the production of VLSI designs has found special placein the integrated circuits industry The high level synthesis process contains two main phases schedulingand resource allocation Resource allocation is further devided into three tasks which are registerallocation functional unit allocation and interconnect allocation In resource allocation phase and in theprocess of register allocation an appropriate storage element is allocated to each variable or signal thatexists in the data flow graph of the circuit Available options for the storage element are latch and flip flop Latches have been used extensively in high performance custom designs while in ASICs mostly flip flopshave been used It s important to extract higher performance in ASIC designs by employing methodologiesused in the custom counterpart In addition to speeding up the execution of the circuit latch consumes lesspower and occupies less area compared to flip flop Latch also is capable of tolerating variations in thedelay of units caused by process variations Each of these advantages is a strong motivation to replace flip flops with latches to upgrade the performance of the circuits In the filp flop based designs eachcombinational block between flip flops can be isolated in view of timing making timing analysis andoptimization very convenient for synthesis based ASICs This is not the case in the latch based design because some combinational blocks may use more than the clock period to compute which has to becompensated for by some other blocks that use less than the clock period Due to the complicated timingbehavior of latches their use makes the design process of the circuits more complicated This is the case inall levels of synthesis including high level synthesis This complicated timing behavior of latches can bemade manageable through the operation scheduling register allocation and control synthesis the key ideacommonly carried in these HLS steps is to prevent latches from being read and written at the same timewhile latches are transparent In this thesis by using the concept of phase step high level synthesis oflatch based architectures have been presented in the form of VHDL codes Using this kind of synthesismakes it possible to decrease the delay of the circuit by optimizing the duty cycle of the clock because theduty cycle the proportion of the clock being high affects the phase step based scheduling and thus itaffects the latency The method to determine the duty cycle that leads to a schedule of the minimum latencyand its code are also presented The high level synthesis of a latch based fifth order EWF filter is presented The results show compared with its flip flop based counterpart structure the execution delay and area ofthe filter are decreased Keywords High level synthesis phase step latch VHDL

بنيمي، الهه السادات

بكارگيري عناصر لچ در سنتز سطح بالاي مدارهاي ديجيتال

استپ فازي , VHDL