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چكيده انگليسي :

Review and Design of a High Speed Switch Mina Ejlali m ejlalikamorin@ec iut ac ir Date of Submission 2012 02 23 Department of Electrical and Computer Engineering Isfahan University of Technology Isfahan 84156 83111 Iran Degree M Sc Language Farsi Supervisor Mohammad Ali Montazeri Montazeri@cc iut ac irAbstract Broadband networks satisfy the need to carry integrated traffic involving different types of information such asvoice video and data Furthermore different services with multiple requirements need specific capabilities to beprovided and guaranteed by broadband networks The architecture of next generation networks has an important effecton making changes in broadband networks and provides these capabilities On the other hand the architecture of broadband networks is highly affected by high speed switches In fact high speed switches are the target technology toachieve the required capabilities The performance demands and changes in IC and VLSI technology have led toemergence of different types of switch architectures The function of switches is to make routing decisions and forward the packets from input to the appropriate output It is possible that multiple arriving packets from different input ports have to be routed to the same output port becausethe incoming traffic is not scheduled to have regular behavior To deal with the output contention switch system usesdifferent types of architectures In first generation switches input ports and output ports were connected using a simpleshared bus Therefore accessing the shared bus became the main bottleneck in switching systems Crossbar switcheshave overcome this problem using N pair inputs and outputs in parallel However implementing crossbar switches isvery expensive As a result different types of multistage switch architectures are proposed to reduce the cost of switchdesign Switching systems in multi plane and multistage architectures is based on making different stages which areconnected through lots of wires Not only these wire connection leads to a delay in the entire communication system butalso they are more expensive than implementing memories as buffers from hardware implementation point of view Shared memory architecture has also its difficulties A shared memory switch has to operate faster than input data ratebecause input ports are time multiplexed to shared buffer However reducing access time to the shared memory isphysically restricted In addition the main area of the chip is occupied with shared memory and its related circuits So shared memory switch architecture would be expensive from hardware implementation point of view In this thesis wedevelop a novel architecture by merging the remarkable properties of multi port memories as well as interleavedmemories to achieve the advantages of both architectures To overcome the cost of multi port memories we useavailable low price FPGAs and their internal block RAMs as the main component for constructing dual port memories Considering various switch design alternatives studying and analyzing of multiple options and exploringadvantages and drawbacks of each solution to design a high switch fabric is very important Each solution has its ownadvantages and drawbacks in terms of performance latency and scalability On the other hand shared bufferarchitecture has high buffer utilization because of sharing a large memory between all input ports However mostpacket buffer designers prefer input buffering due to its ease of implementation shared memory architecture makespossible high switch throughput and it also presents low cell loss probabilities At first a survey on designing high speed switch alternatives and their available solutions are done in this thesis Also this thesis proposes the architectural details of an scalable high speed shared memory switch fabric which isoperating at 20 Gbps The presented architecture is implemented using FPGA technology based on Xilinx s Virtex 4family The rate of the proposed switch is 17

اجلالي، مينا

بررسي و طراحي يك سوئيچ با سرعت بالا

معماري سوئيچ , حافظه مشترك , بانك هاي حافظه , ليست پيوندي , FPGA