پديد آورنده :
احمدي، مهرناز
عنوان :
بكارگيري روش آناليز طيفي در تست مدارهاي منطقي
مقطع تحصيلي :
كارشناسي ارشد
محل تحصيل :
اصفهان: دانشگاه صنعتي اصفهان، دانشكده برق و كامپيوتر
صفحه شمار :
ده، 94ص.: مصور، جدول، نمودار
يادداشت :
ص.ع. به فارسي و انگليسي
استاد راهنما :
مسعود سيدي
استاد مشاور :
رسول دهقاني
توصيفگر ها :
سيگنال ديجيتال , بردار تست , تست پذيري
تاريخ نمايه سازي :
28/3/91
تاريخ ورود اطلاعات :
1396/09/14
رشته تحصيلي :
برق و كامپيوتر
دانشكده :
مهندسي برق و كامپيوتر
چكيده فارسي :
به فارسي و انگليسي: قابل رويت در نسخه ديجيتالي
چكيده انگليسي :
59 Using spectral analysis in logic circuits testing Mehrnaz Ahmady m ahmady@ec iut ac ir Date of Submission 2011 09 9 Department of Electrical and Computer Engineering Isfahan University of Technology Isfahan 84156 83111 Iran Degree M Sc Language FarsiSupervisor Sayed Masoud Sayedi m sayedi@cc iut ac irAbstract In the process of design and fabrication of integrated circuits it is very important that the circuits be testable andtested at different stages of IC production to make sure that they work properly With ongoing growing ofintegrated circuit sizes the design and fabrication of VLSI circuits is becoming more complicated as well as thetest vector generation and testing of the circuits which are very time consuming and costly and in some cases evenimpractical So it is very important to find new techniques of test vector generation which are not only precise butalso low complex For higher level descriptions of circuits the test vector generation is simpler This indicatesgenerating test vectors for RTL description level is easier than that of gate description level In this work for testvector generation of logic circuits first an algorithm implemented in VHDL language is presented The algorithmthat can be used for all description levels of the circuits finds the smallest test vector set of the circuits with highfault coverage Stuck at 0 and stuck at 1 faults are modeled in the algorithm Then another algorithm which worksbased on controllability and observability parameters of the circuit nodes is presented This algorithm which is morepractical and can be used for larger circuits is employed for gate level description of circuits This algorithm whichis also written in VHDL language first calculates the controllability to 0 and to 1 values of the circuit nodes andthen based on that finds appropriate test vectors for the circuit Both algorithms are applied on some test circuits andthe results are presented Spectral analysis can be used to simplify test generation Spectral analysis of a digitalsignal is to find its properties and sequences A digital circuit if considered as a black box can be identified via itsinput and output signals Accordingly test vectors generated for register level description faults have properties thatcan be used to reveal some characteristics of the gate level structure of the circuit These properties can be extractedthrough spectral analysis and used in generation of gate level test vectors By using spectral analysis and Walshtransform a digital signal is decomposed into a set of unique bit streams of orthogonal functions in which magnitudeof each coefficient of bit streams shows the amount of correlation exist between the digital signal and thecorresponding bit stream By maintaining the prominent coefficients and changing nonessential coefficients a newset of coefficients are obtained By applying reverse Walsh transform to this set of coefficients some new testvectors are generated These vectors are appended to the primary test set The new test vector set even though isoriginated from a RTL level vector set shows high fault coverage for gate level faults By using the algorithmpresented in this work for some test circuits different test vectors for different number of faults in RTL leveldescription are generated and based on them and through spectral analysis new test vectors are generated and faultcoverage improvement is calculated The results are presented and the influencing factors on the improvement arediscussed Keywords Digital signal test vector spectral analysis testability VHDL
استاد راهنما :
مسعود سيدي
استاد مشاور :
رسول دهقاني