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چكيده انگليسي :

13 Balanced Application Scheduling and Power Management of Variation Affected CMPs Mahdi Kalbasi m kalbasi@ec iut ac ir Date of Submission 2012 Department of Electrical and Computer Engineering Isfahan University of Technology Isfahan 84156 83111 Iran Degree M Sc Language FarsiSupervisor Pejman Khadivi Massoud Reza Hashemi pkhadivi@ec iut ac ir hashemim@cc iut ac irAbstractWith scaling of chip manufacturing technology process variation divergence of process parameters fromtheir nominal values gets worse on one hand process variation results in differences in delay and powerconsumption of the die s transistors On the other hand with advances in technology designers can put moreprocessor cores on a die and we could have Chip MultiProcessors CMPs In a CMP a consequence ofwithin die process variation is that the individual cores consume different power and offer differentmaximum frequencies Therefore considering a variation affected CMP as a homogeneous one is a wrongassumption In such a system if variation not considered in task allocation the scheduling would besuboptimal In contrast if variations observed as an effective parameter in task allocation algorithms asignificant improvement in throughput and power consumption is available Similarly ignoring variations inCMP power management even global DVFS based power management techniques is not best Instead DVFS can be performed in per core manner or in the dynamic voltage frequency islands It is significant thatsuch scheduling and power management algorithms can be easily carried out in today s commercialprocessors For example Intel s Foxton technology for the monitoring and control power of cores is used intheir processors Furthermore the AMD quad core Barcelona processor provides per core frequencyassignment Many techniques are offered to improve the performance of heterogeneous CMPs byoptimization of application scheduling algorithms However CMP can be designed heterogeneous from thefirst These algorithms try to allocate each application to the best suited core which run the application inless time and with minimal power consumption As far as we know in none of them disrupt the balance ofthis system is not considered Indeed in such methods some parts of the chip have a great load while otherparts are mostly idle As a result distribution of temperature will be asymmetric at the chip wide andtherefore we will have hotspots In addition leakage power relies on the temperature exponentially and willincrease largely Moreover passing threshold temperature will activate dynamic thermal management DTM techniques which influence performance dramatically both cases have been described in Another issue isthat assigning cores for applications due to increasing performance may be opposed with fairness Due touniformity of core s capabilities in a heterogeneous CMP applications execute on cores with differentperformance Therefore scheduling strategy should allow all the applications to use high performance coresequally as much as possible In this thesis we propose a scheduling method for CMPs that in addition toprocess variation considers balancing of the CMP in task allocation Hence processor resources used fairly and temperature distributed chip wide Moreover to optimize power consumption per core DVFS is used To increase the speed of optimization algorithm uses of DVFS with very low resolution have suggestedwhich makes the search space small and overheads of finding the voltage frequency optimal values reduce Keywords Application Scheduling DVFS Chip MultiProcessors Process Variation Power Management Balancing

كلباسي، مهدي

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