عنوان :
مطالعه تراشه هاي بينايي چند- منظوره و طراحي و ساخت يك تراشه نمونه
مقطع تحصيلي :
كارشناسي ارشد
محل تحصيل :
اصفهان: دانشگاه صنعتي اصفهان، دانشكده برق و كامپيوتر
صفحه شمار :
نه، 102ص.: مصور، جدول، نمودار
استاد راهنما :
مسعود سيدي
استاد مشاور :
آرمين خليلي سه بردان
توصيفگر ها :
حسگر تصوير هوشمند CMOS , پردازش درون _ پيكسلي , FILL factor
تاريخ نمايه سازي :
1394/06/02
تاريخ ورود اطلاعات :
1396/10/04
رشته تحصيلي :
برق و كامپيوتر
دانشكده :
مهندسي برق و كامپيوتر
چكيده فارسي :
به فارسي و انگليسي
چكيده انگليسي :
103 Study of general purpose vision chips and design and implementation of a sample circuit Mohammad Sajad Noohi Ms noohi@ec iut ac ir Date of Submission 2015 09 22 Department of Electrical and Computer Engineering Isfahan University of Technology Isfahan 84156 83111 Iran Degree M Sc Language FarsiSupervisor Sayed Masoud Sayedi m sayedi@cc iut ac irAbstract Nowadays image processing has attracted much attention especially in design of real time image processing systems because of the need for high speed along with low area andlow power consumption features Vision chips are developed to achieve these requirementswhere the main idea is mostly to integrate the image sensor section and the processingcircuit on a single chip mostly in a CMOS technology In terms of implementation visionchips are divided into three categories of digital analogue and mixed mode In terms ofapplication they can be divided into general and specific purpose chips The digital visionchips have normally the benefits of higher speed precision stability and noise immunity but their analogue counterparts have lower power consumption and occupy smaller area Since multitask vision chips have the capability of programmability and are able toaccomplish various signal processing tasks these chips have higher power consumption They also occupy more area and offer lower speed and lower fill factor comparing to thespecific purpose chips The aim of present work is to design a multitask digital processing circuit wichperforms in pixel processing in high speed and with low power consumption and it has arelatively high fill factor For the processings which can be performed in a parallel anSIMD architecture is used The processings such as erosion dilation edge detection andcombination of them are performed synchronously in each pixel and in parallel so theprocessing time is independent of the image size Another processing that the proposedcircuit performs is asynchronous propagation among the pixels that is used for the holefilling and image reconstruction The speed of this processing is dependent on the imagesize and the state of the propagation In the proposed circuit each main synchronousprocessing is performed in one clock cycle that causes a relatively high increase in theprocessing speed This means that the frame rate is equal to the working frequency In theproposed circuit a dynamic comparator is used in each pixel The designed layout for onepixel shows the fill factor is about 27 5 The simulation and experimental results of anarray of 32 64 of the proposed pixel verify the performance of the circuit Keywords 1 Vision chip 2 CMOS smart image sensor 3 In pixel processing 4 Multitask processing4 Fill factor
استاد راهنما :
مسعود سيدي
استاد مشاور :
آرمين خليلي سه بردان