طراحي مدارات فليپ-فلاپ كم توان با قابليت حفظ مقدار به فرم سلولهاي ديجيتال استاندارد

چكيده انگليسي :

Low Power State Retention Clocked Storage Element Standard Cell Design Hossein Karimiyan Alidash Hkarimiyan@ec iut ac ir Hossein karimiyan@yahoo com June 23 2010 Department of Electrical and Computer Engineering Isfahan University of Technology Isfahan 84156 83111 Iran Sayed Masoud Sayedi Supervisor M Sayedi @cc iut ac ir Hossein Saidi Supervisor HSaidi@cc iut ac ir Rasoul Dehghani Advisor Sayed Mahmood Modares Hashemi Department Graduate Program Coordinator Abstract Continuous scaling of CMOS technology increases device density and enhances circuit performance in terms of computing power The price of these enhancements is design complexity and more power dissipation As more transistors are integrated with each new technology leakage energy is also going to dominate the dynamic power consumption Generation and distribution of the required power removing dissipated heat and reliability concerns are at the forefront of current problems faced by IC designers In the highly pipelined synchronous VLSI chips employing high performance clocking sub system is a crucial need Energy consumption of the clocking sub system which is composed of clock distribution networks and clocked storage elements is a large fraction of total dynamic power dissipation In the other hand due to aggressive shrinkage of device dimensions reduced node capacitance and the smaller amount of stored charge radiation effect and soft error problem in digital circuits are becoming increasingly important as the CMOS technology progresses from sub micrometer scale to nanometer scale This research presents two groups of dual edge triggered static flip flops suitable for low power applications In the first group storage elements are proposed which have dual edge triggering and state retention capability The proposed circuits deploy reduced swing clock and data to manage dynamic power Furthermore they employ clock and power gating during idle mode to eliminate dynamic power and reduce static power while retaining the state The static structures of the circuits make them feasible to be used in designs employing variable frequency to reduce power consumption The second group of the proposed circuits is aimed to reduce soft error probability that make them more robust to particle hit effect on both the internal nodes and the external logic The hardening method is based on the use of redundant feedback loop to protect internal nodes as well as the schmitt trigger and skewed CMOS gates to filter out transients resulting from particle hit on combinational logic To further improve the performance the proposed circuits use pulsed clocking technique which results in less timing overhead and negative setup time HSPICE post layout simulation conducted for 90nm CMOS technology indicates that in addition to state retention test capability and soft error hardening the proposed designs are comparable to other high performance flip flops in terms of power delay product device count and leakage power The simulation result reveals that the hardened circuits are able to recover from almost any single particle strike on internal nodes and tolerates input transients up to 120ps of duration Besides presenting the analyses and characterizations of the proposed circuits their design in the standard cell form useable in the standard digital design flow is also presented Keywords Clocking low power flip flop dual edge triggering static latch state retention design for soft error mitigation reliability

كريميان عليداش، حسين

طراحي مدارات فليپ-فلاپ كم توان با قابليت حفظ مقدار به فرم سلولهاي ديجيتال استاندارد

طراحي توان پايين , لچ , حفظ حالت , مدارهاي مقاوم در برابر تشعشع