طراحي مدارهاي ديجيتال توان پائين با استفاده از خانواده هاي ديناميكي كنترل شونده با اطلاعات

چكيده انگليسي :

Design of Low Power Digital Circuits Using Data Driven Dynamic Logic Shirin Pourashraf shirinpourashraf@gmail com Date of Submission 2011 4 26 Department of Electrical and Computer Engineering Isfahan University of Technology Isfahan 84156 83111 Iran Degree M Sc Language Persian Supervisor Sayed Masoud Sayedi m Sayedi@cc iut ac ir Abstract In today s advanced fabrication technologies implementation of a complete system with high processingspeed and low consumed area on a single chip is possible But for implementation of some operations likemultiplication due to the number of needed transistors and also the overall circuit power dissipation thechallenge still exists and the design of such circuits is critical In dynamic circuits the excessive loading ofclock signal that connected to the flip flops and dynamic gates leads to high power consumption especiallyin high frequency circuits In Data Driven Dynamic Logic structures D L family compared to otherdynamic logic families the clock distribution network is reduced and instead of clock signal the input signalsare used to control the precharge and Evaluation phases This not only reduces the problems caused by theclock signal buffering and clock routing but also reduces the power losses in the circuit However alongwith less power consumption compared to other dynamic structures the precharge and also often theevaluation phases are slower in D L structure Therefore the structure needs some modification to reduce theproblem of low speed Today in every general purpose microprocessor structure a part of the hardware isallocated to the divider section Also in the processing of digital signals in the three dimensional graphicapplications high speed units that perform division operation are necessary and the demand for them isincreasing In general the sequential format of the division operation leads to high latencies in the circuits Using high radix numbers especially in the SRT dividers which are considered among the fastest divisionalgorithms in VLSI circuits reduces the number of steps efficiently that consequently reduces the latencyand subsequent power consumption Using look up table to select the quotient which is performed in mostalgorithms has lead to the complexity of the SRT dividers implementation causing that a considerable partof the consumed power be related to the tables Employing some methods to reduce the size of the tables oreven remove them can considerably increase the speed of the divider and also reduce the powerconsumption In this thesis besides reviewing the division algorithms and the logic families structures theimplementation of a 16bit radix 4 SRT divider based on a modified D L family structure is presented Theaim of the work is reduction of the required steps to perform the algorithm latency delay and powerconsumption For implementation the TSMC 180 nm technology is used The divider has pipelined structureand its latency is equal to 10 half cycles Simulation results show that in tt corner and 27 C consumedenergy is about 364 Pico joule and delay is lower than 885 Pico second The energy consumption andefficiency of the proposed circuit by applying different inputs in five corners tt ss ff fs and sf of the processand temperature variations from 55 C to 125 C are evaluated Compared with its dynamic version theresults show lower power consumption and higher speed for the proposed structure The circuit also iscompared with other SRT dividers Also an estimation of the area and performance of the proposed circuit inthe layout level has been presented Key Words SRT dividers Latency Data Driven Dynamic Logic Structures Reduction of energy consumption Speed

پوراشرف، شيرين

طراحي مدارهاي ديجيتال توان پائين با استفاده از خانواده هاي ديناميكي كنترل شونده با اطلاعات

تقسيم كننده ي SRT , Latency , ساختارهاي ديناميكي كنترل شونده با اطلاعات كاهش انرژي مصرفي , سرعت عملكرد