بكار گيري تكنيك Logical Effort در طراحي و بهينه سازي سرعت واحدهاي محاسباتي

چكيده انگليسي :

Using Logical Effort Technique in Design and Speed Optimization of Arithmetic Units Fatemeh Karami Horestani f karamihorestani@ec iut ac ir Date of Submission 2011 05 23 Department of Electrical and Computer Engineering Isfahan University of Technology Isfahan 84156 83111 Iran Degree M Sc Language FarsiSupervisor Sayed Masoud Sayedi M Sayedi@cc iut ac irAbstractIn the process of electronic circuits design it is necessary to estimate various parameters so that based onthem an appropriate circuit can be selected The most important parameters are speed power consumptionand area The speed parameter can be estimated by using some models for transistors and gates Thesemodels besides simplicity need to be enough accurate in order to give an accurate estimation of circuitbehavior Using a simple and appropriate model is important because it can help to estimate the delaybefore the simulation step and before accurately designing the circuit and also can help to find appropriatetopologies to decrease the delay Logical Effort is a simple model that can rapidly estimate the delay of thecircuit with enough accuracy By using this model the minimum delay can be estimated only by knowingthe number of the stages the path effort parameter and the parasitic delay of the logic gates Therefore itcan be done before determining the sizes of the circuit gates The sizes can be determined later based on theestimated delay Another advantage of the model is that the delay calculation is independent of technologyand manufacturing process With recent rapid advances in multimedia and communication systems real time signal processing hasfound high importance in many applications Adders are used as fundamental building blocks in manydigital processors So their speed has important role in the processors speed A typical structure of an adderis the Ripple Carry Adder The delay of this adder is mainly due to the generation and propagation of thecarry signal from the lower bits to the higher bits Many techniques have been proposed to decrease thisdelay Multiplier units are also widely used in many digital processing systems Improving the speed andperformance of this unit effectively increases the speed of the system In fact the highest operation time within the basic digital operation units usually determines by the multiplier units Therefore designing afast multiplier to achieve high speed processing units for today s applications will be important Columncompression multipliers such as Dadda and Wallace structures are among the fastest multipliers In thesetwo structures the delay is proportional to the logarithm of the operand word length In the array multipliersthis dependency is linear and as a result the delay is much higher The two structures also have lowerhardware and area In this thesis first a 64 bit Carry Look ahead Adder is designed and then its performanceis optimized by using the Logical Effort technique The 1 79 ns delay in the original structure has beenchanged to 1 23ns in the optimized structure Also with some modification in the carry generation units andusing logical effort technique the delay has been reduced to 1 017 ns The power consumption has beenreduced to about 45 in both cases Afterward a new multiplier structure based on column compressionmultiplier structure is proposed Compared to Dadda structure the speed and area are improved The delayis reduced to about 5 to 10 percent and transistor count is reduced to about 4 5 percent With applyinglogical effort technique further improvement in speed is obtained and the delay is reduced to about 15 Simulations are done with Hspice using TSMC 0 18um CMOS technology with 1 8V power supply Keywords 1 delay models 2 critical path 3 logical effort 4 ripple carry adder5 carry look ahead adder 6 column compression multipliers

كرمي هرستاني، فاطمه

بكار گيري تكنيك Logical Effort در طراحي و بهينه سازي سرعت واحدهاي محاسباتي

مدل هاي تاخيري , مسير بحراني , تلاش منطقي , جمع كننده ي تموج نقلي , ضرب كننده هاي متراكم ساز ستون