8993

8338

كارشناسي ارشد

معماري كامپيوتر

اصفهان: دانشگاه صنعتي اصفهان، دانشكده برق و كامپيوتر

1392

ص.چهارده،111ص.: مصور،جدول،نمودار(رنگي)

ص.ع.به فارسي و انگليسي

مسعودرضا هاشمي

حسين سعيدي

18/3/93

علي فانيان، احسان يزديان

مهندسي برق و كامپيوتر

ID8338

Design and Implementation of a Scalable Switch with FPGA Technology Mehdi Amini mehdi amini@ec iut ac ir Date of Submission 2014 03 16 Department of Electrical and Computer Engineering Isfahan University of Technology Isfahan 84156 83111 Iran Degree M Sc Language PersianSupervisor Masoud Reza Hashemi Hashemim@cc iut ac irAbstract In this research the architecture of a scalable switch has been proposed The structure of the designdepends on the technology that is being used to implement the switch In fact due to the advantages of FPGA Field Programmable Gate Array technology such as availability low cost and short implementation timewith respect to the ASIC Application Specific Integrated Circuit design which has limitations such ascomplex design process and high cost The FPGA technology has been selected to implement the scalablearchitecture as a convenient way Although the FPGA technology has some limitations such as limited number of pins and resources memory CPU and etc during the design process Therefore due to this technology and existinglimitations the architecture of a scalable switch will be proposed and to test the proposed structure architecture a switch on a Spartan6 family FPGA platform has been implemented In this research requiredresources and design constraints for the implementation of large scale switches on the FPGA platform hasbeen studied So we are going to be able to estimate and identify the required resources and their limitationsand to choose the right FPGA platform to design and implement large scale switches The main purpose of the proposed structure in this research is that each of the design blocks can beimplemented on a separate FPGA chip and then each of these chips based on a proposed design scheme canbe hierarchically integrated on a board to make the large scale switch But since there is no such a board withsuch properties in the first stage of the test process the whole design theme has been downscaled in whichthe switching blocks are 5x5 and in two layers makes our switch In the main structure the size of blocks willbe assigned with respect to the available resources on the FPGA chip In the following thesis first it has been tried to study the available solutions to design a switch Then toreach the goals on designing a scalable switch and to consider the challenges in the design process a samplehierarchical switch on a FPGA platform has been implemented The mentioned switch has been implementedon Spartan6 FPGA family boards Keywords Switch Architecture Scalability Hierarchical FPGA

مسعودرضا هاشمي

حسين سعيدي

علي فانيان، احسان يزديان